Software

Software#

The software framework has a modular structure that reflects the firmware and adds extra layers to make hardware interface user friendly. It loosely follows Register Abstract Layer (RAL) concepts. All the layers are automatically created based on a YAML configuration file.

_images/basil_layers.png

Note

The diagram shows USB as the physical interface, but TCP/IP (via Ethernet and SiTCP) is now the more common choice for new designs. Both are supported.

The Dut class parses a YAML configuration file and instantiates all modules in order: transfer layer first, then hardware drivers, then registers. Each entry has a name and a type that maps to a Python class in the corresponding layer package.

Transfer Layer (TL)#

Implements communication interfaces. Each entry in the transfer_layer list defines a connection to hardware.

transfer_layer:
  - name: intf
    type: SiTcp
    init:
      ip: 192.168.10.16
      udp_port: 4660
      tcp_port: 24

Available types (see basil/TL/):

  • SiTcp – Ethernet via SiTCP

  • SiUsb / SiUsb3 – USB 2.0/3.0

  • Serial – RS-232 / USB-serial

  • Visa – PyVISA for GPIB/USB/serial instruments

  • Socket – Raw TCP socket

  • SiSim – Simulation interface (cocotb)

class basil.TL.TransferLayer.TransferLayer(conf)[source]#

Transfer Layer implements minimum API needed access to hardware. On error raise IOError.

init()[source]#

Initialize and connect to hardware.

read()[source]#

Read access.

Return type:

None

write(data)[source]#

Write access.

Parameters:

data (iterable) – array/list of bytes

Return type:

None

Hardware Layer (HL)#

Implements drivers for FPGA firmware modules and external lab devices. Each entry in the hw_drivers list references a transfer layer by name via interface, and FPGA modules are addressed via base_addr.

hw_drivers:
  - name: gpio
    type: gpio
    interface: intf
    base_addr: 0x30000
    size: 8

  - name: spi
    type: spi
    interface: intf
    base_addr: 0x20000

  - name: seq
    type: seq_gen
    interface: intf
    base_addr: 0x10000
    mem_size: 8192

Available FPGA module types are documented in detail on the Modules page. Basil also includes drivers for a wide range of lab instruments, including power supplies, electrometers, oscilloscopes, function generators, climate chambers, chillers, mass flow controllers, temperature/humidity sensors, wafer probers, and Arduino-based peripherals. The full set of drivers can be found in basil/HL/.

class basil.HL.HardwareLayer.HardwareLayer(intf, conf)[source]#

Hardware layer (HL) base class.

wait_for_ready(timeout=None, times=None, delay=None, delay_between=None, abort=None)[source]#

Determine the ready state of the device and wait until device is ready.

Parameters#

timeoutint, float

The maximum amount of time to wait in seconds. Reaching the timeout will raise a RuntimeError.

timesint

Maximum number of times reading the ready state.

delayint, float

The number of seconds to sleep before checks. Defaults to 0.

delay_betweenint, float

The number of seconds to sleep between each check. Defaults to 0.

abortThreading.Event

Breaking the loop from other threads.

Returns#

True if state is ready, else False.

Register Layer (RL)#

Implements Register Level Abstraction. Allows user/control software to work on DUT registers without thinking about underlying levels. Each entry in the registers list references a hardware driver by name.

registers:
  - name: SEQ
    type: TrackRegister
    hw_driver: seq
    seq_width: 8
    seq_size: 8192
    tracks:
      - name: CLK_INIT
        position: 0
      - name: CLK_SAMP
        position: 1

Available types (see basil/RL/):

  • StdRegister – Standard bit-field register

  • TrackRegister – Sequencer track register

  • FunctionalRegister – Functional register

class basil.RL.RegisterLayer.RegisterLayer(driver, conf)[source]#