Modules

Driver

class basil.HL.gpio.gpio(intf, conf)

GPIO interface

reset()

Soft reset the module.

Driver

class basil.HL.spi.spi(intf, conf)

Implement serial programming interface (SPI) driver.

get_data(size=None, addr=None)

Gets data for incoming stream

get_en()

Gets state of enable.

get_repeat()

Gets Number of repetitions of sequence with delay ‘wait’ (if 0 –> repeat forever)

get_size()

Get size of shift register length

get_wait()

Gets time delay between repetitions in clock cycles

is_done()

Get the status of transfer/sequence.

reset()

Soft reset the module.

set_data(data, addr=0)

Sets data for outgoing stream

set_en(value)

Enable start on external EXT_START signal (inside FPGA)

set_repeat(value)

If 0: Repeat sequence forever Other: Number of repetitions of sequence with delay ‘wait’

set_size(value)

Number of clock cycles for shifting in data ex. length of matrix shift register (number of pixels daisy chained)

set_wait(value)

Sets time delay between repetitions in clock cycles

start()

Starts the shifting data

Driver

class basil.HL.seq_gen.seq_gen(intf, conf)

Sequencer generator controller interface for seq_gen FPGA module.

Driver

class basil.HL.pulse_gen.pulse_gen(intf, conf)

Pulser generator

get_en()

Return info if pulse starts with a fixed delay w.r.t. shift register finish signal (true) or if it only starts with .start() (false)

set_delay(value)

Pulse delay w.r.t. shift register finish signal [in clock cycles(?)]

set_en(value)

If true: The pulse comes with a fixed delay with respect to the external trigger (EXT_START). If false: The pulse comes only at software start.

set_repeat(value)

Pulse repetition in range of 0-255

set_width(value)

Pulse width in terms of clock cycles

start()

Software start of pulse at random time

Driver

class basil.HL.seq_rec.seq_rec(intf, conf)

Sequencer receiver controller interface for seq_rec FPGA module.

Driver

class basil.HL.cmd_seq.cmd_seq(intf, conf)

FEI4 Command Sequencer Controller Interface for cmd_seq FPGA module.

Driver

class basil.HL.fei4_rx.fei4_rx(intf, conf)

FEI4 receiver controller interface for fei4_rx FPGA module

Driver

class basil.HL.fast_spi_rx.fast_spi_rx(intf, conf)

Fast SPI interface

reset()

Soft reset the module.

Driver

class basil.HL.tlu.tlu(intf, conf)

TLU controller interface

Driver

class basil.HL.tdc_s3.tdc_s3(intf, conf)

TDC controller interface

Driver

class basil.HL.sram_fifo.sram_fifo(intf, conf)

SRAM FIFO controller interface for sram_fifo FPGA module.

property FIFO_INT_SIZE

Get FIFO size in units of integers (32 bit).

fifo_sizeint

FIFO size in units of integers (32 bit).

get_FIFO_INT_SIZE()

Get FIFO size in units of integers (32 bit).

fifo_sizeint

FIFO size in units of integers (32 bit).

get_data()

Reading data in SRAM.

arraynumpy.ndarray

Array of unsigned integers (32 bit).

get_fifo_int_size()

Deprecated Get FIFO size in units of integers (32 bit).

fifo_sizeint

FIFO size in units of integers (32 bit).

get_fifo_size()

Deprecated Get FIFO size in units of bytes (8 bit).

fifo_sizeint

FIFO size in units of bytes (8 bit).

get_read_error_counter()

Deprecated Get read error counter.

fifo_sizeint

Read error counter (read attempts when SRAM is empty).

get_size()

Deprecated

Driver

class basil.HL.fadc_rx.fadc_rx(intf, conf)

Fast ADC channel receiver

set_align_to_sync(value)

Align data taking to a synchronization signal, reset signal is the synchronization signal (hard coded connection in Verilog source code)

set_single_data(value)

Driver

class basil.HL.i2c.i2c(intf, conf)

Implement master i2c programming interface driver.

property is_ready

raises ExceptionType

IOError

Transfer not acknowledged.

read(addr, size)

Read access.

Parameters

• addr (char) – i2c slave address

• size (int) – size of transfer

Returns

data byte array

Return type

array.array(‘B’)

write(addr, data)

Write access.

Parameters

• addr (char) – i2c slave address

• data (iterable) – array/list of bytes

Return type

None